The future of SUNY Poly's 450 mm silicon wafer project is uncertain as two of the five member companies involved have announced that they have stopped working with the consortium known as the G450C.
450 mm Silicon Wafers Project
According to Extreme Tech, a few years ago, several high-end companies have created a consortium with the aim of moving from 300 mm to 450 mm silicon wafers. Moving to larger wafers was, historically, one of the critical ways that foundries improved yields and cut prices.
More recently, in the silicon industry, the charge on wafer size has been led by companies like Intel. Currently, 58 companies still operate 200 mm fabs, while 23 firms have 300 mm fabs in production. The cost savings of 300 mm wafers can be further extended by 450 mm wafers, but uncertain rollouts and high costs appear to have doomed the endeavor.
GlobalFoundries, Samsung, Intel, IBM and TSMC have launched collectively several years ago the Global 450 Consortium (G450C) in partnership with The Colleges of Nanoscale Science and Engineering (CNSE) at SUNY Polytechnic Institute (SUNY Poly). This was a collaboration over five years involving a $4.8 billion-dollar endeavor to work with suppliers on 450 mm ecosystem development, develop tools and create appropriate infrastructure for the future deployment of 450 mm wafers.
Why 450mm Silicon Wafer Initiative Is Delayed
The task to develop the 450 mm ecosystem was a difficult one, since larger wafers means different tools. Lithography equipment and EUV tools are significantly more expensive than traditional 193 nm ArF lasers. According to Times Union, two of the five major firms involved in the G450C are stopping the collaboration with the project after the end of the five-year program.
In terms of total production capacity, the larger 300 mm wafers are more popular than 200 mm wafers, but they only limited to specific areas of the market. Power management devices, image sensors, NAND flash, DRAM, GPUs, CPUs and other high volume technologies are typically built on 300 mm wafers. Where lower total volumes are expected, 200 mm wafers are used.
Major contract silicon manufacturers such as TSMC make a significant percentage of their income using out of date nodes that haven't been cutting-edge in over a decade. Older equipment is paired with many of these older nodes in order to minimize the purchase of new hardware and keep them cost-effective.
Of course, there are advantages to using larger wafers. In case that the foundry is able to keep its wafers-per-hour production rate on 450 mm wafers close to its 300 mm wafer production rate, they it can manufacture much more chips per hour. Assuming that the foundry utilization rate is high and the semiconductor economy is healthy, this would help reduce costs.
But now, with no clear roadmap for the technology and multiple companies pulling out of G450C, it seems that 450 mm wafers are going to be delayed or even pretty much dead. Companiew are still focused on ramping up 300 mm wafers at various foundries, 450 mm pilot programs have ended and no semiconductor company is still championing 450 mm wafer research or deployment. Machine replacements and high costs appear to have neutralized any argument for improving wafer utilization or superior cost savings in the long term.
