NVIDIA currently has seven job positions that are open for applications, all of which require unique responsibilities and certain requirements. While most require the applicant to work on-site when hired, some listings allow for remote work.
Senior Low Power Design Verification Engineer
Santa Clara, CA
What You'll Do:
As a Senior Low Power Design Verification Engineer, you'll be required to work with Low Power Architecture, Design, and Software teams in order to learn about next-gen features for future products. Your expertise will be needed for developing test benches, infrastructure, and test plans.
These are to verify various power management solutions for the products of NVIDIA, which includes contributing creative ideas to improve power-aware DV methodologies, along with influencing EDA vendors to improve simulations and debug efficiencies.
Skill Requirements:
Experience in MSEE/MSCE (or equivalent) along with a background in ASIC design verification. Background in Low Power architectures or verification is an advantage.
A minimum of three years of industry experience and understanding of low-power design techniques (multi VT, Clock gating, Power gating, Block Activity Power, Dynamic Voltage-Frequency Scaling, etc.)
Knowledge about processor architecture and related power management design or DV techniques.
Fluency in Verilog, SystemVerilog, and understanding of UVM.
Should be knowledgeable in programming languages like C and C++.
Experience with Verdi as well as strong debugging skills.
Experience in writing or maintaining scripts or Makefile that builds the simulation program.
Strong skills in planning and organization, as well as interpersonal skills.
The applicant must be self-motivated and works well with others.
Scripting abilities in Python or Perl are an advantage, along with knowledge in power intent in UPF format.
Salary Range: $124,000 - $247,250 (depending on location, experience, and pay of employees in the position)
Vice President, Silicon Engineering and Sourcing
Santa Clara, CA
What You'll Do:
Mainly, you will drive and participate in the development of system/process improvements and supply chain solutions across organizational teams. You will also collaborate with internal partners to manage silicon suppliers.
This is to ensure production readiness, assurance of supply and delivery, cost, performance, and overall quality in support of NPI, MP builds, and sustaining operations. You will be tasked to develop and execute global supply chain strategies, including driving Requests for Quotes or Supply (RFX).
In addition to that, you will oversee the Foundry Engineering and Silicon Failure Analysis groups, as well as technical investigative actions for highly complex customer issues, production qualification issues, and yield improvement items to ensure proper and prompt resolution.
You will serve as the point of contact for foundries with product-level needs, as well as collaborate with internal partners to manage foundries relationships, strategy, and contractual/SOW engagements.
You will also be tasked to ensure delivery, cost, performance, and overall quality to pre-aligned key performance indices (KPIs) in support of new test chips, prototypes, and products. You'll be required to report to the project's senior management team at regular intervals.
Other than that, you're required to oversee the analysis of failures and the identification of failure modes at both die and sub-assembly levels, along with leading or supporting root cause analysis of field failures and drive design/foundry improvements.
Skill Requirements:
Ph.D. or Masters in electrical engineering, chemical engineering, chemistry, semiconductor physics, or material science or equivalent experience.
15+ overall years of experience with 7+ years in management.
Expertise and proven track record of working with semiconductor foundries/fabs and taking products/processes from lab to fab.
Experience with bringing up emerging technologies in fabs/foundries.
Understanding semiconductor equipment, process control, data analysis, reliability, and yield and/or supply chain, is a strong plus.
Technical Management experience with a global engineering team.
Good familiarity with commercial and operational concepts such as contract negotiations, demand forecast, order placement, wafer costs, and wafer and chip yields
Have a network of semiconductor foundries and fabs contacts.
Up to 25% of travel, domestic and international.
Salary Range: $360,000 - $517,500
Senior ASIC Design Engineer
Santa Clara, CA
What You'll Do:
As a Clocks team member, you will be collaborating with other architects, ASIC designers, and verification engineers to design high-frequency clocks, as well as the software and product design team to debug SOC clock silicon bugs in our new products.
You'll need knowledge of System Verilog to verify the clocks design, engage with multiple teams, and design the SOC clocks to satisfy all the architectural constraints. With your team, clock information should be delivered to the SOC verification, timing, and DFT teams.
Skill Requirements:
BS in Electrical Engineering or equivalent experience (MS preferred).
7+ years of relevant work experience.
Ability to thrive in a dynamically changing environment.
Experience in RTL design (Verilog), verification, and logic synthesis.
Strong coding skills in Perl or other industry-standard scripting languages.
Knowledge of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
Implementing on-chip clocking networks is a bonus.
Salary Range: $156,000 - $287,500
Senior SOC Design Engineer
Santa Clara, CA
What You'll Do:
As the Senior SOC Design Engineer, you'll get to build complex GPU and Tegra chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT, and other teams.
You'll be tasked to define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner, as well as identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to tackle them.
Skill Requirements:
BS or MS in Computer or Electrical Engineering or equivalent experience
5 plus years of proven experience in chip design, specializing in SOC integration and design automation.
Excellent analytical and problem-solving skills.
Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation.
Strong coding skills in Perl, Python, or other industry-standard scripting languages.
Great communication and teamwork skills to interact within the team and across functional teams to build consensus.
Experience in synthesis, pairing, and physical design is a plus.
Salary Range: $124,000 - $247,250
Senior Compiler Engineer
Cambridge
What You'll Do:
You'll be working with a geographically distributed partner organization to understand, modify and improve CPU Compiler SW at NVIDIA, along with contributing new features and optimization techniques targeting NVIDIA Grace CPUs engaging with upstream and open source communities.
You'll be tasked to develop compiler SW that should be optimized for performance. You will be part of a team at the center of AI, HPC, and data center technologies, as well as contribute towards the development of next-gen compute.
Skill Requirements:
BS or MS degree in Computer Science, Computer Engineering, or related field or equivalent work experience
Experience with compiler development or a related academic project.
Knowledge of Language Front-Ends or Compiler optimization techniques and code generation modules.
Strong hands-on C++ programming skills
Excellent verbal and written communications skills
Salary: Highly competitive with a comprehensive benefits package
Senior Silicon Security Architect
Remote
What You'll Do:
You be doing research, design, development, and implementation of architecture solutions with both hardware and software, meeting internal and external security requirements and standards.
Part of the job is applying innovative hardware security primitives to enable next-generation secure software extensions supported by hardware, as well as collaborating with partners on the implementation of open-source software.
You'll also be working across the company to guide the direction of Silicon security, TEE, working with hardware, software, research, and product teams, as well as customers and partners to identify and address security issues and threats.
In addition to that, you will be tasked with architectural modeling, validation, microarchitectural definition, following standards bodies, and developing infrastructure enabling trusted platforms using hardware security methods.
Skill Requirements:
BSc, MS, or Ph.D. in Electrical Engineering, Computer Science or Computer Engineering, or equivalent experience.
7+ years of relevant experience.
First-hand work experience with the ASIC design architecture of SoCs and designing hardware security for embedded devices.
Have directly worked on several of the following:
Computing platform security, threat models and mitigation techniques.
RISC-V architecture, Root-of-trust, and security processors.
Distributed key management API and Cryptographic accelerators and standards.
Familiarity with embedded systems and programming low-level firmware.
Experience in Security-by-design hardware and principles of privileges.
Programming and debugging fundamentals across languages such as Verilog, Python/Perl scripting, ARM assembly, and C/C++.
The ability to work in a dynamic collaboration-oriented team is required and strong communication skills and a real passion for working as a team are essential.
